1. Technical Field
Embodiments of the present invention are related to the field of electronic devices, and in particular, to errors in electronic devices.
2. Description of Related Art
Single event upsets (SEUs), also referred to as soft errors (SERs), are radiation-induced transient errors in digital systems caused by high energy particles such as neutrons generated from cosmic rays and alpha particles from packaging material. For designs manufactured at advanced technology nodes (130 nm, 90 nm, and so on), SEUs are gaining in importance. Hence, soft errors may be significant for microprocessors, network processors, high end routers and network storage components that target enterprise and applications with very high reliability, data integrity and availability. More specifically, bistables (latches and flip-flops) may be major contributors to the system-level soft error rate.
Scan Design-For-Testability (DFT) has become a de facto test standard in the industry because it enables an automated solution to high quality production testing at low cost. In addition, scan DFT may be used for post-silicon debug activities because it provides access to the internal nodes of an integrated circuit. Scan implementations in major high-end microprocessors involve significant circuitry and clock signals that are used only during post-silicon debug and production testing. These resources generally are unused during functional system operation, although they occupy additional area and draw additional leakage power. Scan DFT utilizes scan cells, such as a full-hold, 4-latch scan cell and a 3-latch scan cell for flip-flop based designs or a 2-latch scan cell for latch-based designs.
Referring to FIG. 1, a conventional full-hold scan cell 10 is shown. The scan cell 10 provides a full shadow of the machine state and enables non-intrusive operation while an integrated circuit (IC) chip (not shown) is running or while the system clocks are frozen. The scan cell 10 includes a system flip-flop 12 having a first latch PH2 and a second latch PH1 adapted to receive a data input signal DATA and two phases of a system clock CLK1 and to generate an output signal Q. The cell 10 further includes a scan circuit 14 having a shadow flip-flop 16 with a first latch LA and a second latch LB and interface circuits between the flip-flops 12 and 16. The cell 10 has a test and a functional mode of operation.
Referring to FIG. 2, during the test mode, scan clocks SCA and SCB are applied alternately to the scan cell 10 to shift in (scan in) a test pattern or scan-in signal SI into the latches LA and LB. Next, a signal UPDATE is applied to move the contents of latch LB to latch PH1 so that the test pattern is written into the latch PH1, allowing the test pattern to be applied to a downstream combinational logic circuit (not shown). Next, the inverted clock CLK2 is applied to latch into the latch PH2 a system response to the test pattern received from an upstream combinational logic circuit (not shown), followed by applying the non-inverted CLK1 to move the latched contents of the latch PH2 to the latch PH1. Finally, the signal CAPTURE is applied to move the contents of latch PH1 into latch LA. The system response or scan-out signal SO may now be scanned out by alternately applying clocks SCA and SCB. Referring to FIG. 3, during the functional mode, clocks SCA and SCB and signals CAPTURE and UPDATE are set low, and system clock CLK1 is applied.